From FPGA prototype to ASIC implementation

EXA has developed a fully functional FPGA-based prototype of the REBECCA platform. The prototype uses two Alinx AXKU15 FPGA boards: one emulates the REBECCA ASIC, while the other represents the external FPGA that hosts the hardware accelerators and peripherals not implemented directly in the ASIC. Together, the two boards provide a complete environment for validating the functionality and system-level integration of the REBECCA platform before silicon is available.

The design process of the REBECCA platform followed an FPGA-first approach. After the initial draft of the architecture of both the hardware and software components that constitute the overall REBECCA platform, an FPGA prototype was first produced taking advantage of the quick design process, the availability of essential IP components and a multitude of available physical implementation platforms, each with its own merits for the project (e.g. a development board like the aforementioned Alinx board that enabled the development and testing of peripherals and custom external interfaces and PCIe-based FPGA accelerator cards that enabled the remote access of the prototypes from both hardware and software developers). The result was the production of a series of FPGA designs that provided an accurate implementation of the envisioned ASIC-based final REBECCA hardware platform that enabled developers of hardware accelerators to validate their designs with the main system components (RISC-V CPUs, AXI4 communications and I/O) and software developers to implement their low-level and application-level components on the actual hardware with much higher accuracy and speed than having to resort to software simulation environments.

From EXA’s perspective, this FPGA platform provided the means to test and validate the bootloaders, low-level firmware and the OS bring up for the platform. On the hardware front, among other components, EXA was able to validate the memory interface to external HyperRAM memory ICs. EXA developed a dedicated FMC module populated with eight HyperRAM memory chips. The module connects to the FPGA board through an FMC connector, allowing the FPGA to communicate with the HyperRAM devices and emulate the HyperRAM memory interface expected in the final REBECCA system. As such, the memory controller and its interaction with the rest of the design has been tested and verified before ASIC fabrication.

Following a stable and verified FPGA system, EXA has focused on transitioning the REBECCA design from the FPGA prototype to an ASIC-synthesizable implementation. This required replacing several FPGA-specific IP blocks with ASIC-synthesizable alternatives, including cache memories, FIFOs, and I/O buffers. Additional RTL changes were also necessary because FPGA and ASIC synthesis and simulation tools may interpret and optimise the same RTL differently.

The first required adaptations were identified during RTL simulation, particularly in peripherals such as the SD controller. Post-synthesis simulation then revealed further issues that required additional RTL refinements. Many were related to the more aggressive optimisations applied by ASIC synthesis tools. Clock- and reset-related RTL in particular had to be carefully implemented, since logic that is not described appropriately can be optimised away or transformed in ways that affect the intended functionality.

Following several iterations of simulation, synthesis, verification, and RTL refinement, the required adaptations were completed. This marks a major project milestone: the REBECCA chip design has now been submitted for physical implementation.