Publications
Open-access publications, abstracts of presentations, and other scientific papers
ACKNOWLEDGMENT: REBECCA project is supported by the Chips Joint Undertaking and its members, including the top-up funding by National Authorities under grant agreement n° 101097224. Funded by the European Union. Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the European Union or the granting authority. Neither the European Union nor the granting authority can be held responsible for them.
Silent Data Errors:
Sources, Detection, and Modeling
Adit Singh / Sreejit Chakravarty / George Papadimitriou / Dimitris Gizopoulos
Silent Data Corruptions:
Microarchitectural Perspectives
George Papadimitriou / Dimitris Gizopoulos
A DSP shared is a DSP earned: HLS Task-Level Multi-Pumping for High-Performance Low-Resource Designs
Giovanni Brignone / Mihai T. Lazarescu / Luciano Lavagno
Assurance of Software-Intensive Medical Devices: What About Mental Harm?
Jose Luis de la Vara / Barbara Gallina / Antonio Fernández-Caballero / Jose Pascual Molina / Arturo S. García / Clara Ayora
Generic Architecture for Multisource Physiological Signal Acquisition, Processing and Classification Based on Microservices
Roberto Sánchez-Reolid / Daniel Sánchez-Reolid / Clara Ayora / José Luis de la Vara / António Pereira / Antonio Fernández-Caballero
Model-driven gap analysis for the fulfillment of quality standards in software development processes
Giovanni Giachetti / José Luis de la Vara / Beatriz Marín
Assessment of the quality of the text of safety standards with industrial semantic technologies
Jose Luis de la Vara / Hector Bahamonde / Clara Ayora
Estimating the Failures and Silent Errors Rates of CPUs Across ISAs and Microarchitectures
Dimitris Gizopoulos / George Papadimitriou / Odysseas Chatzopoulos
Impact of Voltage Scaling on Soft Errors Susceptibility of Multicore Server CPUs
Dimitris Agiakatsikas / George Papadimitriou / Vasileios Karakostas / Dimitris Gizopoulos / Mihalis Psarakis / Camille Bélanger-Champagne
To Spike or Not To Spike: A Digital Hardware Perspective on Deep Learning Acceleration
Fabrizio Ottati / Chang Gao / Qinyu Chen / Giovanni Brignone / Mario R. Casu / Jason K. Eshraghian / Luciano Lavagno
gem5-MARVEL: Microarchitecture-Level Resilience Analysis of Heterogeneous SoC Architectures
Odysseas Chatzopoulos / George Papadimitriou / Vasileios Karakostas / Dimitris Gizopoulos
SimPoint-Based Microarchitectural Hotspot & Energy-Efficiency Analysis of RISC-V OoO CPUs
Odysseas Chatzopoulos / Maria Trakosa / George Papadimitriou / Wing Shek Wong / Dimitris Gizopoulos
Energy-Efficient Object Detection: Impact of Weight Clustering for Different Arithmetic Representations
Martí Caro / Jaume Abella
Harpocrates: Breaking the Silence of CPU Faults through Hardware-in-the-Loop Program Generation
Nikos Karystinos / Odysseas Chatzopoulos / George-Marios Fragkoulis / George Papadimitriou / Dimitris Gizopoulos / Sudhanva Gurumurthi
Advancing Cloud Computing Capabilities on gem5 by Implementing the RISC-V Hypervisor Extension
George-Marios Fragkoulis / Nikos Karystinos / George Papadimitriou / Dimitris Gizopoulos
Hybrid Convolutional Neural Networks with Reliability Guarantee
Hans Dermot Doran / Suzana Veljanovska
Reliability of CNN Execution - A Novel Application of the Single Protected Channel Pattern
Hans Dermot Doran / Suzana Veljanovska
An Early-Stage Workflow Proposal for the Generation of Safe and Dependable AI Classifiers
Hans Dermot Doran / Suzana Veljanovska
An Energy-Efficient GeMM-Based Convolution Accelerator With On-the-Fly im2col
Jordi Fornt / Pau Fontova-Musté / Martí Caro / Jaume Abella / Francesc Moll / Josep Altet
NN2FPGA: Optimizing CNN Inference on FPGAs With Binary Integer Programming
Roberto Bosio / Filippo Minnella / Teodoro Urso / Mario R. Casu / Luciano Lavagno / Mihai T. Lazarescu
Optimizing the Longhorn Cloud-native Software Defined Storage Engine for High Performance
Konstantinos Kampadais/ Antony Chazapis / Angelos Bilas
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Silent Data Corruptions: The Stealthy Saboteurs of Digital Integrity
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(PDF) Assurance of Software-Intensive Medical Devices: What About Mental Harm?
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Estimating the Failures and Silent Errors Rates of CPUs Across ISAs and Microarchitectures
-
Impact of Voltage Scaling on Soft Errors Susceptibility of Multicore Server CPUs
-
gem5-MARVEL: Microarchitecture-Level Resilience Analysis of Heterogeneous SoC Architectures
-
SimPoint-Based Microarchitectural Hotspot & Energy-Efficiency Analysis of RISC-V OoO CPUs
-
Harpocrates: Breaking the Silence of CPU Faults through Hardware-in-the-Loop Program Generation
-
Advancing Cloud Computing Capabilities on gem5 by Implementing the RISC-V Hypervisor Extension