ACKNOWLEDGMENT: REBECCA project is supported by the Chips Joint Undertaking and its members, including the top-up funding by National Authorities under grant agreement n° 101097224. Funded by the European Union. Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the European Union or the granting authority. Neither the European Union nor the granting authority can be held responsible for them.
Full-Custom FPGA-based AI Accelerator Architectures for Edge Computing: Crack Detection in Harbor Structures
Prepared by FORTH
The REBECCA platform is aimed (among other goals) to facilitate AI-on-the-Edge for a broad spectrum of applications. One such REBECCA application (Use Case 4) is the inspection of harbor structures for cracks. Neural network models have been developed and trained by REBECCA partners ALM and ASXL, implemented in SW on RISC V by SML and implemented in HW on FPGA technology by FORTH (full-custom approach) and by POLITO (framework-based approach).
This blog post is on the FORTH AI Accelerators.
Full-custom vs. Framework based AI Accelerators on FPGAs
The full-custom approach offers unrestricted design space (under the CNN model and target FPGA requirements). It is amenable to more design optimizations, at the cost of (substantially) higher design time. The framework-based approach has the limitations of the framework scope, but within these limitations it offers faster design times, easier re-targeting of the design, and hence more opportunities for design space exploration and designer productivity. Both approaches are very useful. REBECCA encompasses both approaches for AI computing on-the-Edge through the FORTH and the POLITO AI accelerators, respectively.
The FORTH AI Accelerator: One Accelerator or three?
The FORTH AI Accelerator implements already trained CNN models for harbor inspection. All models were developed by REBECCA partners ALM and ASXL, and they are towards the same end application, however, they have different characteristics. There exist substantial differences, both in the model itself and in the target technology. In parallel with the FORTH AI Accelerator, SML implements these models in software, and this software implementation is under integration with the third FORTH AI Accelerator. The work of SML includes additional training of the YoloV8 ALM/ASXL model, using the ALM/ASXL training data, and this version is implemented on the third FORTH AI Accelerator.
It is not just the numbers – tradeoffs among the accelerators
Although the figure, above, shows some quantitative characteristics of the three accelerators, there are substantial differences. To illustrate, whereas the original UNET-based CNN developed and trained by ALM and ASXL had great results in detecting cracks, the computational demands combined with the number of slices that would be needed to process an entire image led to the adaptation of a Yolo-based approach, which offered similar accuracy in a less computationally-intensive manner. In terms of a full-custom AI Accelerator architecture, the algorithm change led to substantial design changes, keeping however many of the datapath elements at hand. To illustrate:
The first and the second FORTH AI Accelerators run the entire CNN with all of its layers (which in YoloV11 was 99 layers). This necessitated compaction of the weights with K-means. Multiple simulations led to the appropriate number of index bits for memory compaction with acceptable accuracy loss.
The second AI Accelerator had 128 processing elements (PEs), each capable of performing a 3X3 convolution, one line at a time, for a latency of roughly 11 cycles per convolution (9 multiplications and 9 additions – including a bias addition) and an effective achievable parallelism of more than 100X.
The third AI Accelerator could not employ such a wide datapath due to the smaller ALINX FPGA vs. the VCU FPGA. A datapath of 16 was chosen. Although the processing part of the datapath is the same as the larger, 128-PE one, all memory subsystems needed to be re-designed. Due to memory limitations, not all weights and biases could be kept on-FPGA, and as result the third accelerator processes one layer at a time, with weights which are not compressed.
The third accelerator, based on YoloV8, is integrated with the SML-developed software version of the same model. The RISC V – based software makes calls to the Accelerator, one layer at a time.
As of July, 2026, the third accelerator is in the integration stages on the ALINX-based REBECCA Emulation platform, which has all of the characteristics of the final REBECCA system except that the RISC V processor is implemented on a (separate from that of the Accelerator) FPGA.
Many more tradeoffs exist, however, the REBECCA know-how on how to perform AI Edge computing with FPGAs is very extensive. As a result, there exist opportunities to use this technology on many FPGA-based AI-on-the-edge accelerators, besides the inspection of harbor structures.