Rebecca chips successfully passed tapeout

Rebecca has passed every signoff check and the netlist is frozen. After months of work, the design is now with the foundry. Rebecca is an edge AI system-on-chip (SoC). It is built as a chiplet,  meaning a single die does not have to carry every workload on its own. Two of them will sit in the same package and share the work over a Die2Die link. From a software perspective, this looks like one large system.

The design was a joint effort with multiple partners. The IPs were developed independently and integrated together into the Rebecca die. Exapsys developed the RISC-V based processing system and several IPs along with top-level integration. IMEC developed the neuromorphic accelerator and the University of Lund developed Near Memory Processing (NMP) accelerator. Fraunhofer implemented Bunch-of-Wires Die2Die interface and was responsible for the physical implementation with synthesis and Place & Route (PnR).

The controller/processing side is a four-core OpenPiton subsystem running at 500 MHz. The cores communicate over an on-chip network and reach the rest of the system through an AXI crossbar. The specialized accelerators sit beside the cores.  The neuromorphic accelerator for spiking neural networks which is highly power efficient and reprogrammable for learning on the device. The NMP performs its multiply accumulate operations inside its own memory, which reduces internal data traffic during convolutional neural network inference. Two HyperRAM channels with four memories each running at 150 MHz DDR provide the accelerators the bandwidth they need. Apart from these, the chip has a set of interfaces that includes Die2Die, chip to FPGA, SD card, QSPI flash, two UARTs, GPIO, JTAG and control inputs providing flexibility to interact with the chip.

The Rebecca die is highly memory-dominated. There are 223 SRAM instances across 12 configurations. The chip is built in GlobalFoundries 22FDX, a 22 nm FD-SOI process on a ten-metal stack. The lower metal layers are for standard cells, intermediate layers for routing and the top layer for power distribution with an aluminium layer on top for the pads. The die is 3.0 × 3.8 mm and is assembled flip-chip on copper pillar bumps rather than wire bonds, which keeps the connections short. This configuration spreads the supply current across the whole surface of the die. The figure shows the layout of the chip and provides and overview where each major IP is located.

Implementation was run through the Cadence tools: Genus for synthesis, Innovus for PnR, Tempus for timing signoff, Conformal for equivalence checking, Xcelium for simulation and Calibre for physical verification. Synthesis turned the RTL into roughly 2.6 million standard cells, which were then placed and routed around the 223 memory macros and the PLLs.

We expect silicon back at the start of next year. The two dies will then be packaged together, connected over the Die2Die link and will then be fitted to the test board that is being finished in the meantime.

The applications for the Rebecca chip can be huge. They include smart appliances, energy generation, infrastructure inspection, avionics, automotive and healthcare domains. Within the project scope, the chip will be used for finding defects in solar panels from a drone, smart fridges, inspecting semiconductor equipment and surveying water infrastructure. Each one runs a vision or AI workload on the device itself rather than sending data somewhere else to be processed and each does so under tight limits on power, latency and safety.