From 8–12 June 2026, in Bologna, Italy, REBECCA project partners Alexandros Ntyrkai, Vasileios Karakostas, and Dimitris Gizopoulos from the National and Kapodistrian University of Athens participated in the RISC-V Summit Europe.
During the event, the team presented their poster titled “Evaluating the Vulnerability of RISC-V CPUs Against Cache Timing Attacks.” Their work focuses on providing systematic support for evaluating the security of RISC-V multicore CPUs against a broad spectrum of cache timing attacks.
Assessing the vulnerability of caches against side-channel attacks is of critical importance when enhanced microarchitectural security is a must-have feature for a multicore CPU implementation. Previous works have proposed various metrics and methodologies to assess such vulnerabilities. However, those works suffer from limitations regarding either the range of target cache attacks, the support for the RISC-V ISA, or rely on in-house simulators.
The goal of this research is to provide support for systematically evaluating RISC-V multicore CPUs against a wide range of cache timing attacks. This support should allow the assessment of both real and simulated systems, enabling early security evaluation in the design phase of the processor using the open-source gem5 microarchitectural simulator.
RISC-V Summit Europe is a leading event that brings together key stakeholders from industry, government, academia, and research communities to shape the future of innovation based on the RISC-V architecture. The strong collaboration between industrial and academic actors plays a crucial role in advancing the RISC-V ecosystem in Europe.
The conference provides a valuable platform to explore both commercial and research applications, making it a key meeting point for those contributing to the next wave of European computing innovation.