In September 2026, Joachim Rodrigues (Lund University, FAU Erlangen-Nürnberg, System-on-Chip at FAU), Sergio Castillo Mohedano (Lund University), and Arturo Prieto (Lund University) participated in the ESSERC 2026 Conference, where they presented two research papers supported by the REBECCA KDT JU project:

- Scalable and Power Efficient Approximate Multipliers for Error-Resilient Applications in 22 nm
Approximate multipliers (AMs) show great potential to achieve substantial area and power savings when replacing their exact counterparts in error-resilient applications. In this paper, we propose an AM architecture, scalable across operand widths. Our 8-bit AM achieves a 1.91% Mean Relative Error Distance (MRED) and a power-area-delay product (PADP) gain of >78.2% over a Wallace multiplier. We also introduce an evaluation methodology focused on post-implementation hardware savings. Beyond standalone benchmarking, measurements of a 22nm chip confirm substantial power reductions of 32.9% when replacing exact multipliers with our AM.

- LUCIA: A Scalable and Versatile 0.82 TOPS/W/mm² Chiplet Architecture for CNN in 22 nm FDSOI.
This paper presents LUCIA, an architecture tailored for multi-chiplet systems optimized for convolutional neural network (CNN) acceleration through configurable hardware engines and distributed workload mapping. The architecture accommodates multiple independent near-memory computing (NMC) units in close proximity to their respective memory banks, tightly coupled with a low-power RISC-V processor. Dedicated memory control units facilitate efficient intra-chiplet and inter-chiplet data transfers, reducing execution time by 34% and consequently improving bandwidth utilization. Fabricated in 22nm FDSOI technology, LUCIA achieves a peak clock frequency of 565MHz and demonstrates an energy-area efficiency of 0.82TOPS/W/mm2, outperforming state-of-the-art implementations in comparable or more advanced technologies.

The team also presented measurement results from a chip incorporating IP developed within the REBECCA project, marking an important step from research towards validation. These contributions showcase REBECCA’s progress in developing power-efficient, scalable, and high-performance computing technologies for next-generation Edge AI.